Customer Spotlight: Viettel Accelerates Design of Its First 5G SoC with Synopsys ASIP Designer
Viettel High Tech had been working on the design of a 5G digital front-end SoC for a gNB 3GPP 5G base station. The engineering team needed to accelerate their time to market for a competitive advantage. In fact, facing a short product development window is not uncommon in this sector. Many organizations began developing their solutions while the 5G standard was still immature, creating the need to keep up with a changing standard without delaying product readiness.
To streamline the process for developing specialized processors for their 5G SoC, the Viettel High Tech team used Synopsys ASIP Designer™, a tool suite that automates and speeds up the process of designing application-specific instruction-set processors (ASIPs).
“ASIP Designer accelerated the design process of Viettel’s first 5G digital front-end SoC to save time and to achieve the desired performance,” noted Le-Thai Ha, Ph.D., a principal engineer at Viettel High Tech. “With ASIP Designer, we can easily adapt designs to new versions of our 5G algorithms with minor changes in the architecture, size, and power consumption. The compiler-in-the-loop and synthesis-in-the-loop design flows that come with ASIP Designer save us months in multiple iterations of changes and optimization. Furthermore, ASIP Designer opens multiple rooms and options for us to optimize the 5G signal processing stream during the SoC development phase and after silicon readiness. We wouldn’t have been able to achieve this flexibility with hard-wired designs.”
Read on for more details about how the Viettel team worked with Synopsys to achieve their goals for their 5G design.
5G Algorithm Performance Requires Hardware Acceleration
5G base station SoCs encompass many sub blocks that are designed in fixed-function RTL. As the 5G standard was defined and requirements weren’t yet standardized, designers began introducing more software programmability into the actual data-processing blocks of these designs. These are typically the radio front-end blocks that digitally correct signals coming in from the antenna. The programmability introduced provided design teams with flexibility to address uncertainties as 5G requirements were being developed.
Software programmability alone is not sufficient to deliver on the throughput and latency demands of 5G. This creates a need for hardware acceleration. The Viettel High Tech team designed data acceleration blocks as well as domain-specific digital signal processors (DSPs). Using the ASIP Designer tool allowed the team to optimize their DSPs for 5G processing.
ASIPs bring together software programmability and application-specific hardware acceleration in one architecture that is optimized for the functions it must implement. Their performance and energy efficiency are better than that of general-purpose processors, while ASIPs also provide flexibility to support multiple algorithmic standards and evolving specifications.
The Viettel High Tech team also wrote algorithms for its 5G digital front-end SoC. Digital pre-distortion algorithms are foundational in wireless communications, increasing the efficiency of RF power amplifiers in 5G base stations. These algorithms must run very fast, hence acceleration is needed. Using ASIP Designer, the engineering team designed the IP blocks to accelerate the performance of their algorithms inside the 5G SoC in a flexible way.
“We employ a true hardware-software co-development environment. Viettel engineers develop 5G algorithms and the ASIP architecture in parallel. The 5G software is validated on the hardware platform at the very early stage of the design. This compiler-in-the-loop design flow offered by ASIP Designer enables Viettel engineers to profile the algorithms and modify the ASIP architecture with ease.”
— Le-Thai Ha, Ph.D., Principal Engineer, Viettel High Tech
Benefiting from a Full Suite of EDA Tools
As an ASIP Designer customer for a number of years, Viettel High Tech works closely with Synopsys technical experts, who provide tool training and support. In addition to ASIP Designer, the team also uses Synopsys design and verification solutions, along with Synopsys Interface and Memory IP solutions. The two companies have built up a close relationship, while the Viettel engineers remain impressed by the quality of the tools and IP.
“We’re pleased with the acceleration features offered by ASIP Designer,” said Dr. Ha. “Instruction-level parallelism, data-level parallelism, and an easy flow to add special instructions help us boost up the ASIP performance. The ASIP cores are easy to implement and verify in the ASIP Designer environment.”
Dr. Ha also noted that “the on-chip debug environment is straightforward to implement and powerful for any kind of software development and hardware-software debugging. Verification at the ASIP level and full-chip level is enabled with supporting tools, which makes the verification process more efficient and less time-consuming.”
Advancing 5G Wireless Communication
The fast connectivity available through 5G wireless communication creates new opportunities for our Smart Everything world. Digital experiences are more enriching and immersive. Businesses are more productive with real-time, data-driven automation. Cities are smarter in how they deliver traffic management, public safety services, and logistics.
“Our vision is to deeply join in the international semiconductor design chain as an innovative design house delivering low-cost and high-performance SoC solutions in the next five years,” noted Mr. Vu-Ha Nguyen, the general director of Viettel High Tech.
Companies like Viettel are at the forefront in advancing 5G communication. With its 5G digital front-end SoC for base stations, developed with Synopsys ASIP Designer, design and verification tools, and IP, the company is doing its part to bring super-fast, reliable connectivity to Vietnam. Along the way, the company is also making good on its aim to help create a digital society that enhances the lives of the country’s people.
Source: https://blogs.synopsys.com/
